 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TECHNICAL DATA IN74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. The IN74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-toHIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. * Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS * Supply voltage range: 1.2 to 3.6 V * Low input current: 1.0 A; 0.1 A at O = 25 N * High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC 14 1 14 D SUFFIX SOIC 1 ORDERING INFORMATION IN74LV74N IN74LV74D IZ74LV74 Plastic DIP SOIC chip TA = -40 to 125 C for all packages PIN ASSIGNMENT RESET 1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V CC RESET 2 DATA2 CLOCK 2 SET 2 Q2 Q2 LOGIC DIAGRAM DATA 1 CLOCK 1 SET 1 Q1 Q1 GND FUNCTION TABLE Inputs Set L H L H H H PIN 20=VCC PIN 10 = GND H H Reset H L L H H H H H L H Clock X X X Data X X X H L X X X Outputs Q H L H* H L Q L H H* L H No Change No Change No Change *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. H= high level L = low level X = don't care Z = high impedance INTEGRAL 1 IN74LV74 MAXIMUM RATINGS * Symbol VCC IIK * 1 2 Parameter DC supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: Plastic DIP * 4 SO * 4 Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds Value -0.5 to +5.0 20 50 35 70 70 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * IO * ICC IGND PD 3 Tstg TL * C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/C from 70 to 125C SO Package: - 8 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, t f DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time except for Schmitttrigger inputs (Figure 1) VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Parameter Min 1.2 0 0 -40 0 0 0 0 Max 3.6 VCC VCC +125 1000 700 500 400 Unit V V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must b e left open. INTEGRAL 2 IN74LV74 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol Parameter conditions VCC V 25C min VIH HIGH level input voltage 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 VI = VIH or VIL IO = -50 A 1.2 2.0 3.0 3.6 3.0 1.2 2.0 3.0 3.6 3.0 * * 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 max 0.3 0.6 0.9 1.1 0.09 0.09 0.09 0.09 0.33 0.1 4.0 Guaranteed Limit -40C to 85C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.34 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.4 1.0 40 125C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 max 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.5 1.0 80 V Unit VIL LOW level output voltage V VOH HIGH level output voltage V VI = VIH or VIL IO = -6mA VOL LOW level output voltage VI = VIH or VIL IO = 50 A V V VI = VIH or VIL IO = 6 mA II ICC Input current Supply current VI = VCC or 0 V VI =VCC or 0 V IO = 0 A V A A * VCC = 3.3 0.3 V AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=t f=6.0 ns) Test Symbol Parameter conditions VCC V 25C min tPHL, tPLH Propagation delay , Clock to Q or Q tPHL, tPLH Propagation delay , Set to Q or Q tPHL, tPLH Propagation delay , Reset to Q or Q tTHL, tTLH Output Transition Time, Any Output CI Input capacitance VI = 0 V or VCC Figures 1,3 VI = 0 V or VCC Figures 2,3 VI = 0 V or VCC Figures 2,3 VI = 0 V or VCC Figures 1,3 1.2 2.0 * 1.2 2.0 * 1.2 2.0 * 1.2 2.0 * 3.0 max 140 45 28 150 44 27 160 47 29 90 20 15 7.0 Guaranteed Limit -40C to 85C min max 160 56 35 170 54 34 180 58 37 110 25 19 min 125C max 180 67 42 190 65 41 200 70 44 130 30 23 ns Unit ns ns ns pF INTEGRAL 3 IN74LV74 CPD Power dissipation capacitance (per flip-flop) VI = 0 V or VCC - 48 - - - - pF INTEGRAL 4 IN74LV74 TIMING REQUIREMENTS(CL=50 pF, t r=t f=6.0 ns) Test Symbol Parameter Puls e Width, Clock, Set or Reset Setup Time, Data to Clock conditions VCC V 25C min tw VI = 0 V or VCC Figures 1,2,3 VI = 0 V or VCC Figures 1,3 VI = 0 V or VCC Figures 2,3 VI = 0 V or VCC Figures 1,3 VI = 0 V or VCC Figures 1,3 1.2 2.0 * 1.2 2.0 * 1.2 2.0 * 1.2 2.0 * 1.2 2.0 3.0 75 25 16 25 16 10 18 9 6 3 3 3 8 18 30 max Guaranteed Limit -40C to 85C min 96 32 20 32 20 13 24 12 8 5 3 3 6 15 24 max 125C min 114 38 24 40 24 15 30 15 9 5 3 3 4 12 20 max ns Unit tsu ns trem Removal Time, Set or Reset to Clock Hold Time, Clock to Data ns th ns fc Clock Frequency MHz * VCC = 3.3 0.3 V V M = 0.5 VCC VOL and VOH are the typical output voltage drop that occur with the output load. Figure 1. Switching Waveforms INTEGRAL 5 IN74LV74 V M = 0.5 VCC Figure 2. Switching Waveforms TEST POINT DEVICE UNDER TEST OUTPUT * CL * Includes all probe and jig capacitance Figure 3. Test Circuit EXPANDED LOGIC DIAGRAM (ONE FLIP-FLOP) INTEGRAL 6 IN74LV74 CHIP PAD DIAGRAM Chip marking 25LV74 12 13 14 1.17 + 0.03 01 07 11 10 09 08 02 Y (0,0) 03 04 05 06 1.32 + 0.03 X Location of marking (mm): left lower corner x=0.520, y=0.865. Chip thickness: 0.46 0.02 mm. PAD LOCATION Location (left lower corner), mm X 0.118 0.118 0.286 0.597 0.895 1.100 1.100 1.100 1.100 0.851 0.540 0.297 0.118 0.118 Y 0.436 0.125 0.125 0.125 0.125 0.125 0.423 0.721 0.930 0.949 0.949 0.949 0.830 0.604 Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol Reset 1 Data 1 Clock 1 Set 1 Q1 Q1 GND Q2 Q2 Set 2 Clock 2 Data 2 Reset 2 VCC Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 Note: Pad location is given as per metallization layer INTEGRAL 7 |
Price & Availability of IN74LV74
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |